The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and system for implementing prioritized refresh of DRAM based cache.
Memory devices are used in a wide variety of applications, including computer systems. Computer systems and other electronic devices containing a microprocessor or similar device typically include system memory, which is generally implemented using dynamic random access memory (DRAM). A DRAM memory cell typically includes, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of a charge. Typically, a first voltage is stored on the capacitor to represent a logic HIGH or binary “1” value (e.g., VDD), while a second voltage on the storage capacitor represents a logic LOW or binary “0” value (e.g., ground).
The primary advantage of DRAM is that it uses relatively few components to store each bit of data, and is thus a relatively inexpensive means for providing system memory having a relatively high capacity. A disadvantage of DRAM, however, is DRAM memory cells must be periodically refreshed as the charge on the capacitor eventually leaks away and therefore provisions must be made to “refresh” the capacitor charge. Otherwise, the data bit stored by the memory cell is lost. While an array of memory cells is being refreshed, it cannot be accessed for a read or a write memory access. The need to refresh DRAM memory cells does not present a significant problem in most applications, however it can prevent the use of DRAM in applications where immediate access to memory cells is required or highly desirable.
Thus, in certain instances, the refresh process involves accessing memory locations corresponding to the same location from which data is needed for system operation. This contention with refresh increases the average latency of the operational accesses. Many refresh algorithms have been devised that attempt to reduce the effect of the refresh process on memory latency. Since, in most cases, it is critical that all memory locations be refreshed within a given period of time, these algorithms systematically work their way through memory addresses from one end to the other. Unfortunately, such a systematic, linear access pattern makes it difficult to avoid instances where refresh and operational accesses conflict.